The present invention relates generally to high-speed multiple data-rate memory interface circuits and more specifically to the calibration of these memory interface circuits. Multiple data-rate interfaces, such as double data-rate interfaces, have become increasingly common. One such type of interface, the double data-rate (DDR) interface, communicates two bits of data per clock cycle at each data line. DDR interfaces are often used with high-speed memory devices, as well as other types of devices.
As DDR interfaces increase in speed, timing margins become smaller and more susceptible to error. For example, the accuracy in the timing between a clock signal and a data strobe signal (DQS) provided by a memory interface to a device such as a memory can be particularly important. Other margins, such as skew among data signals (DQ) and between DQ and DQS signals, also become increasingly important.
Typical DDR signals include DQS and DQ signals provided by a transmitting device and received by a receiver. The transmitting and receiving devices may include integrated circuits, such as FPGAs, and a number of memory devices. Typically, the FPGA or other integrated circuit controls the timing and frequency of operation by providing a clock signal CK to the memory devices.
In some DDR topologies, the clock signal provided by the transmitting device is provided to a number of memory devices in series, that is, to a first memory device, then a second, then a third, and so on. This topology is referred to as a “fly-by” topology and may also be used for control and address signals. The use of this routing means that each memory device receives the clock signal at a different time. The timing of data transfers, both to and from the memory devices, must be adjusted. Further, the CK output and the various DQ and DQS input and outputs may have mismatches in trace length, capacitances, driver strength, and other parameters such that signals on these lines may be skewed relative to each other. Moreover, the timing errors caused by the fly-by topology and these various skews and mismatches typically change during device operation as a function of FPGA temperature and supply voltage.
It is therefore desirable for a memory interface on the FPGA or other integrated circuit to compensate for the different arrival times of the CK signal at different memory devices. It is also desirable to efficiently compensate for skew between CK, DQS, and DQ signals received from and provided to a memory device. Further, it is desirable to be able to update these compensations for changes in temperature and voltage while the device is operating.